1. Field of the Invention
The present invention relates to a wafer-scale integration device including interconnected multiple chips of semiconductor integrated circuits and a fabrication method therefor.
2. Description of the Related Art
In order to meet increasing demand for larger scale integration of semiconductor devices for achieving more functions, higher speeds and smaller gross size, there have been proposed many kinds of methods for integration.
One of the representative methods among them is a multi-chip module. IC (Integrated Circuit) chips are usually encapsulated in a so-called chip carrier, a package, which generally has printed leads on the sides of the carrier. A plurality of the chip-carriers having IC chips therein is mounted on a small ceramic mother board, a substrate, to form a module by conventional hybrid IC technology. A plurality of these modules is further mounted on a big main ceramic board. These multi-chip modules are now used in practical applications. However, with this method, there are problems of cooling the IC chips and wiring the IC chips on the mother board.
The heat dissipated in the IC chips is removed by conduction through the ceramic substrate in the chip-carrier and the ceramic substrate of the mother board, and by forced air flow or liquid flow. Some of the heat is also removed by the main ceramic board. The heat to be removed is now becoming as much as 10 W/cm.sup.2 in a modern system. Therefore, the heat resistance of these ceramic boards can not be ignored. On the other hand, because of the requirement for the high-density wiring, the multi-layer ceramic board is generally employed. The wirings in the multi-layer board are made with refractory metals powders, such as molybdenum or tungsten, which, however, have higher electrical resistance than that of the generally used wirings. The high resistance of the wirings, of course, deteriorates the performance of the module circuit. In addition to these problems, the accuracy of placing the chip carriers can not be satisfactorily achieved because the structure of the chip carrier is not suitable for precise positioning. Thus, the spacing of the layer-wirings can not be made small enough to achieve required high density integration.
On the other hand, as another representative method, monolithic semiconductor fabrication technology also has been employed to attempt to satisfy the above-described requirement for the higher scale integration. Accordingly, the size of the monolithic IC chip is now becoming as big as 5 or 6 inches in diameter, a wafer size, and more than several hundreds of thousands of gates are integrated thereon. This is so-called wafer-scale integration. The scale of this integration is several tens through several hundreds times that of prior art LSICs (Large Scale IC). However, for this scale of integration, there are both technical and economical limits for the following reasons.
The yield (that is, the probability of existence of non-defective chips) of larger-scale IC decreases generally in proportion to the nth power of the yield of lower-scale ICs, where n is the ratio of the scale of the larger-scale IC to the scale of the lower-scale IC. Therefore, when the integration scale of a chip becomes larger, the production yield drastically decreases, causing fatal damages to production cost.
In addition to this yield problem, the cost of masks for the relevant photo-lithography becomes extremely expensive, particularly when the production is a relatively small quantity. According to these facts, the wafer-scale integration is almost impossible for industrial application. Therefore, it has been requested to achieve a well-designed very large-scale integration of ICs which solves the above-described technical problems as well as the cost problems at the same time.